1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to implant processes and more particularly to the fabrication of a pocket or Halo regions.
2) Description of the Prior Art
The semiconductor industry continuously strives to reduce the minimum feature sizes of MOSFETs in integrated circuits. These attempts are essentially driven by the need to produce ICs at lower costs, while retaining or improving circuit functionality and speed. This downscaling can for instance be achieved by reducing the characteristic dimensions of the transistors present on these ICs, and especially the gate lengths, the gate oxide thickness and the junction depths, and by increasing the channel doping levels.
Short MOS transistors generally suffer from the so-called short-channel effect (SCE): the source and drain regions will approach each other when the gate length is reduced. This has an adverse effect on the switching of the transistors in the sense that the switching is less controlled by the gate electrode, which leads to an undesired decrease in the threshold voltage. This adverse effect can be explained by a mechanism which causes the depletion regions around the source and the drain to occupy an increasingly large fraction of the channel region, so that a lower potential on the gate is needed to achieve inversion in the channel.
In the conventional MOSFET scaling scenarios, SCE has been kept within acceptable limits by reducing the junction depths and increasing the channel dopant concentration. These conventional scenarios, however, no longer work for sub-0.18 micron devices, because in these devices the suppression of SCE requires too high a doping level in the channel, which gives rise to junction breakdown.
A proposed solution to this problem is the use of pocket or halo counterdoping implants. Phosphorus, arsenic or antimony ions are used for pockets in PMOS transistors, while boron or indium ions are used for pockets in NMOS transistors. The pocket implants serve to raise the channel doping level in the immediate vicinity of the S/D regions. This leads to a net increase in the channel doping regions when the gate length is reduced, thereby suppressing the influence of the S/D depletion regions for short-channel devices.
In standard MOS processing, and especially in conventional Complementary MOS processing, the pocket implantation step, which is also referred to as the halo implantation step, is combined with the S/D (extension) implantation step. During this combined implantation step, certain areas of the silicon wafers are covered with a patterned resist layer in order to avoid undesired implantation of these areas. For instance, PMOS transistors are covered during formation of NMOS transistors and vice versa. These pocket implants and S/D implants are activated in a single annealing step after removal of the the resist layer. The dopant diffusion during this annealing step determines the distribution of both the pocket dopants and the S/D dopants.
FIG. 8A shows a diagram of ions being implanted into a silicon wafer according to the prior art.
FIG. 8B shows a cross sectional view of the wafer after the ion implant showing three regions: vacancy rich region, projected range region and End of range (EOR) region.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Ser. No. 2003/0013260A1(Gossmann et al.) shows a method of implanting vacancy-generating ions into a preselected region of the body.
U.S. Ser. No. 2003/0096490 A1—Borland, et al.—shows a method for forming a shallow junction in a semiconductor wafer.
U.S. Ser. No. 2002/0001926 A1—Noda—shows a process for an Ir pocket implant.
U.S. Pat. No. 6,537,886b2(Lee) and U.S. 2001/0041432A1 Lee show implant processes.
U.S. Ser. No. 2003/0049917 A1(Noda) shows a multiple I/I and anneal process.
U.S. Pat. No. 6,475,885B1(Sultan) shows a S/D formation with a sub-amorphizing I/I.